The semiconductor industry continues to strive for improvements in the speed and performance of semiconductor devices. Strained silicon technology has been shown to enhance carrier mobility in both n-channel and p-channel devices, and thus has been of interest to the semiconductor industry as a means to improve device speed and performance. Currently, strained silicon layers are used to increase electron mobility in n-channel CMOS transistors. There has been research and development activity to increase the hole mobility of p-channel CMOS transistors using strained silicon germanium layers on silicon.
One approach involves a silicon germanium layer on a silicon substrate, and a silicon capping layer on the silicon germanium layer. Both the silicon germanium and the silicon capping layers are strained if they are thin. The crystalline silicon layer is strained by a lattice mismatch between the silicon germanium layer and the crystalline silicon layer. The silicon germanium layer may be graded to a relaxed or unstrained layer to create more stress in the silicon cap layer. Strained silicon layers have been fabricated on thicker relaxed silicon germanium layers to improve the mobility of electrons in NMOS transistors. Structures with strained silicon on silicon germanium on insulators have been described as well as structures with strained silicon over a localized oxide insulator region. These structures yield high mobility and high performance transistors on a low capacitance insulating substrate.
Known techniques to strain channels and improve carrier mobilities in CMOS devices include improving electron mobility in NMOS transistors using a tensile strained silicon layer on silicon germanium, improving hole mobility using silicon germanium source/drain regions in trenches adjacent to the PMOS transistor to introduce uniaxial compressive stress in the channel of the PMOS transistor, improving electron mobility using silicon-carbide source/drain regions in trenches adjacent to an NMOS transistor to introduce tensile stress, and improving mobility for both NMOS and PMOS transistors using silicon nitride capping layers formed to introduce tensile stress for NMOS transistors and formed to introduce compressive stress for PMOS transistors.
Wafer bending has been used to investigate the effect of strain on mobility and distinguish between the effects of biaxial stress and uniaxial stress. Bonding a semiconductor onto bowed or bent substrates has been disclosed to introduce strain in the semiconductor. Stress can also be introduced by wafer bonding. Packaging can introduce mechanical stress by bending. Compressively-strained semiconductor layers have been bonded to a substrate.